可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經銷商處購買 |
|---|---|---|---|---|
| 74LV08APW | 74LV08APWJ | 935690645118 | SOT402-1 | 訂單產品 |
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Click here for more information74LV08APW
Quad 2-input AND gate
The 74LV08A is a quad 2-input AND gate.
Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 2.0 V to 5.5 V
Maximum tpd of 10 ns at 5 V
Typical VOL(p) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C
Typical VOH(v) > 2.3 V at VCC = 3.3 V, Tamb = 25 °C
Supports mixed-mode voltage operation on all ports
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA per JESD 78 Class II
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV08APW | 2.0?-?5.5 | CMOS | ± 12 | 4.3 | 45 | 4 | low | -40~125 | 140 | 7.5 | 66 | TSSOP14 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LV08APW | 74LV08APWJ (935690645118) |
Active | 74LV08A |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT402-1_118 |
文檔 (10)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LV08A | Quad 2-input AND gate | Data sheet | 2024-01-30 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| lv08a | 74LV08A IBIS model | IBIS model | 2019-01-08 |
| Nexperia_document_leaflet_Logic_LV-AT_201903 | LV-A(T) logic family | Leaflet | 2019-03-19 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SOT402-1_118 | TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2025-01-16 |
| 74LV08APW_Nexperia_Product_Reliability | 74LV08APW Nexperia Product Reliability | Quality document | 2024-06-16 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LV08APW | 74LV08APWJ | 935690645118 | Active | SOT402-1_118 | 2,500 | 訂單產品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LV08APW
Quad 2-input AND gate
從安世半導體購買
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